A binary rate multiplier is a circuit having as its input signals a multiplier value N and a frequency to be multiplied, f.sub.0, which produces output signals at a rate N times f.sub.0. There are two basic types of binary rate multipliers. The first type includes an m-stage binary ripple counter (or divider) used with a 2.sup.m times f.sub.0 system clock. The set output signal from each of the m counter stages primes a separate AND gate, each of which is enabled by a corresponding bit from the binary multiplier value, N. The output signals from the AND gates are combined in a single OR gate to produce the output signals at a frequency of N times f.sub.0. The output signals from this type of binary rate multiplier are unevenly spaced throughout a period of the input signal f.sub.0. An example of this type of binary rate multiplier is explained in greater detail in Electronic Design 11, May 23, 1968, pp. 78 et seq.
A second type of binary rate multiplier utilizes a presettable counter which is incremented by the circuit output signals. A non-zero value in the presettable counter primes an AND gate which is enabled by a clocking signal which has a rate greater than the maximum desired value of N times f.sub.0. When N output signals at the internal clock rate have been produced, the output gate is disabled until the next period of f.sub.0 which presets the counter, usually to the value of the complement of N and the process continues. The output signals in this second type of binary rate multipliers are produced at the internal clock rate and are groups at the beginning of each output period.
The present invention is used with a binary rate multiplier of the second type to space the ouput signals substantially evenly throughout the period represented by the reciprocal of f.sub.0.